1. Field of the Invention
The present invention relates to a serial access memory with securing of the write operations. The invention is particularly suited to floating-gate memories and one-time programmable memories.
2. Discussion of the Related Art
EPROM or EEPROM type floating-gate memories, when they are non-programmed, are in an intermediate state between a "0" logic level and a "1" logic level. To write in these cells, high voltages are used to shift the charges from the intermediate level to the desired level "0" or "1". To enable writing to be done again in these cells, it is highly advisable to erase them beforehand, namely to reset the memory cells to the intermediate level. For EPROM type memories, this is done by exposure to ultraviolet radiation. For EEPROM type memories, it is done by using voltages that are slightly greater than those used for programming, with a different bias.
These floating-gate memories are often used in portable electronic card devices such as chip cards. The pads in these connection devices tend to get worn out through frequent actions of connection and disconnection. This wearing out of the pads has the effect of introducing a big parasitic pulse in these pads. When a reading operation is erroneous, it is enough to redo it to obtain efficient reading. However, when there is an erroneous write operation, it is sometimes not possible, and at best is difficult to correct it.
In the case of a write operation, it is therefore preferable not to write erroneous data. Indeed, one-time programmable memories cannot be reprogrammed, the EPROM memories need an ultraviolet radiation source to be erased, and the EEPROM type memories used in chip cards do not routinely have the load pumps needed for reprogramming.
The sources of erroneous write operations due to parasitic pulses coming from the pads generally result in positive or negative pulses at the terminals providing access to the memory. In the case of serial memories, the parasitic pulses may affect the data elements directly or indirectly. This means that the parasitic pulses may affect the data elements or the control signals of the memory, making it carry out random type writing operations.
Embodiments of the invention propose to remedy the problem of writing erroneous data due to the presence of parasitic pulses in the control signal. Indeed, in embodiments of the invention, it is not possible to write a data element if an error is detected in the synchronization of the control signals. For this purpose, a writing operation will be performed only if it is ascertained that a signal for the selection of the memory changes after the reception of the data elements.